Synopsys AI Chip Design Hits Major Milestone With Azure Cloud, STMicro And SK Hynix
Machine Learning, or what the industry generally refers to as AI, has permeated many industries as a driving force that enables new-found capability and performance, such that it appears as though nearly everything is going “smart.” As I reported in September, even semiconductor chip design itself is being optimized with AI, and it’s making big strides in design efficiency for next-gen chip tech. Electronic Design Automation tools (EDA) bellwether, Synopsys, recently chalked up its 100th chip tape-out with top industry players like STMicroelectronics, SK Hynix and Microsoft stepping out in endorsement of the company’s DSO.ai (Design Space Optimization) place and route technology, which is also available as cloud software tools as a service (SaaS) on Microsoft Azure.
The place and route optimization step in semiconductor chip design is a simple concept to understand. First, engineers design the circuits, logic, memory structures, etc., then these blocks need to be mapped to a silicon mask set that ultimately can be patterned on a wafer for chip production. That mapping and connecting of various circuits has historically been very labor-intensive, taking a team of engineers weeks or months to achieve optimal performance, silicon area real estate and power efficiency, or “PPA” — Performance, Power and Area optimization. However, with re-enforcement machine learning, Synopsys DSO.ai can now deliver better results in far less time with far fewer design engineering human resources required.
Recently, I spent some time with Stelios Diamantidis, Distinguished Architect and Head of Strategy, Autonomous Design Solutions at Synopsys, learning about the advances of its DSO.ai tool as a part of its overall EDA tools suite and strategy. Stelios pointed out that, while DSO.ai automation for place and route has achieved a major milestone with its 100th commercial chip tape-out, the company is also striving to utilize AI for other resource-intensive areas of chip design as well, like verification and even logic circuit design optimization itself.
“AI’s ability to explore broader design spaces is accelerating our customers’ relentless drive towards better PPA and higher productivity with fewer engineering resources,” noted Shankar Krishnamoorthy, GM for the EDA Group at Synopsys. “We’ve monitored the first 100 commercial tape-outs by customers using Synopsys DSO.ai and the results are compelling. Whether they’re designing in the cloud, on-premise or a hybrid of the two, it’s clear that in every case, designers are seeing significant gains from optimized designs delivering better results and faster time-to-market. The cloud-side is particularly exciting as deploying Synopsys AI technology at scale in data centers ushers an exciting new era for designers everywhere.”
In addition, STMicroelectronics recently fired up an Arm core-based design effort on Synopsys Cloud AI tools and claimed that, “using the Synopsys DSO.ai design system on Microsoft Azure, we increased PPA exploration productivity by more than 3x, allowing us fast implementation of a new Arm core, while exceeding power, performance and area goals,” said Philippe d’Audigier, system-on-chip hardware design director at STMicroelectronics.
Memory chip technology juggernaut SK Hynix had this to say about the new Synopsys AI-drive tools as well. “Delivering high-performance, robust memory products at industry-leading volumes demands intensive optimization, which has traditionally been highly human intensive,” noted Junhyun Chun, head of SoC (System on Chip) at SK hynix. “Synopsys DSO.ai brings a huge amount of design team efficiency, giving our engineers more time to create differentiated features for our next generation of products. It’s also driving fantastic results as demonstrated in a recent project where DSO.ai delivered a 15% cell area reduction and a 5% die shrink.”
When it comes to the highly competitive semiconductor industry and high chip wafer costs these days, a 5% die shrink is far more significant than perhaps it might sound. And with the widely reported chip design engineer shortage that exists today, the reclaimed human resource hours that STMicro realized are also a huge win for the company as well as other big name chip players, and start-ups alike. As an aside, the SK Hynix design was performed with an on-prem instance of Synopsys DSO.ai.
Finally, though a 100th chip tape-out milestone is big news for AI chip design technologies in general, Microsoft, which is not always quick to step out in support of broader industry efforts, had this to say. “Microsoft is committed to democratizing advanced chip design, so it was a natural move for us to host the Synopsys DSO.ai design system on Azure,” said Jean Boufarhat, corporate vice president, engineering, Azure Hardware and Infrastructure at Microsoft. “With AI-powered chip design on Azure, companies can leverage cloud-scaling to boost productivity and optimize very large solution spaces like high-performance computing.”
Clearly, Microsoft has some skin in the game here, highlighting its Azure cloud infrastructure as a service products, but again 3rd party endorsements are typically hard to come by from Redmond. Synopsys is currently the top EDA tools leader in the market according to recent stats, and the company is leading the charge by harnessing the power of machine learning and AI to usher in new levels of efficiency and performance.